1. Field of the Invention
The present invention generally relates to circuits and more particularly relates to ring oscillator circuits.
2. Description of Related Art
Persons of ordinary skill in the art will understand terms used in this disclosure, such as MOS (metal-oxide semiconductor) transistor, including NMOS (n-channel metal-oxide semiconductor) transistor and PMOS (p-channel metal-oxide semiconductor), “gate,” “source,” “drain,” “saturation region,” as used in connection with a MOS transistor, and basic concepts for electronic circuits, such as: “voltage,” “current,” “inverter,” “oscillation,” “frequency,” “period,” “phase,” and “hysteresis.” Terms and basic concepts like these are apparent from prior art documents, e.g. text book such as “Design of Analog CMOS Integrated Circuits” by Behzad Razavi, McGraw-Hill (ISBN 0-07-118839-8), which reflect the understanding of persons skilled in the art, and thus will not be explained in detail here.
As depicted in FIG. 1A, a prior art quadrature output ring oscillator 100 comprises four primary inverters 110, 120, 130, and 140 configured in a four-stage ring topology, and four feedforward inverters 150, 160, 170, and 180 configured to provide four feedforward paths, which operate to sustain an oscillation of an output signal comprising four phases: V0, V90, V180, and V270. This principle of the quadrature output ring oscillator 100 is known in prior art, and need not be described further herein.
An exemplary timing diagram for the quadrature output ring oscillator 100 is depicted in FIG. 1B. Here, T is a period of the output signal that comprises the four phases (V0, V90, V180, and V270). As shown in FIG. 1B, V90 leads V0 in timing by 90 degrees; V180 leads V90 in timing by 90 degrees; and V270 leads V180 in timing by 90 degrees. Note that a time delay of T/4 corresponds to 90-degree phase shift for the output signal.
In the quadrature output ring oscillator 100 of FIG. 1A, feedforward inverters 150 and 160 form a first positive feedback loop to force V0 and V180 to have opposite levels and thus opposite phases, while feedforward inverters 170 and 180 form a second positive feedback loop to force V90 and V270 to have opposite levels and thus opposite phases. However, a regenerative nature of the two positive feedback loops also introduces hysteresis that adversely impedes toggling of the output signal and thus slows down the oscillation. In addition, each primary inverter shares a common output node with a feedforward inverter, but the input of the primary inverter is different from that of the feedforward inverter and a condition of contention may occur. For instance, primary inverter 110 shares a common output V0 with feedforward inverter 150, but the input of primary inverter 110 (i.e., V270) is different from the input of feedforward inverter 150 (i.e., V180). As shown in FIG. 1B, V180 and V270 are opposite in level and thus contending in time interval 101 (where V180 is low but V270 is high) and time interval 102 (where V180 is high but V270 is low). The contention not only slows down the oscillation, but also wastes power.